Electric motors fulfill a host of needs, providing motion in rotating or linear form in every aspect of our daily lives. Motors are used in everything from common household appliances to sophisticated electronic systems and computers. Many of the earliest motor types developed more than 100 years ago are still in use.

With many more sophisticated applications arising, motor control has become an increasingly important issue, requiring the development of more complex technologies to deliver needed improvements in performance, energy consumption and safety. While small motors are those most often used in applications requiring extreme precision, large motors such as those used in robots frequently perform very complex tasks in real time.

need for efficiency

High performance motor control has a significant effect on overall consumption of energy. A recent U.S. Department of Energy study reported that electric motors consume nearly 60 percent of all electrical power generated in the country. Considering industry alone, the figure increases to more than 75 percent. Refrigeration for homes and offices (another motor-intensive set of applications) consumes almost 10 percent of the world's energy, while the electric motors running systems in heating, ventilation and air conditioning in commercial buildings account for approximately 50 percent of a building's total electric bill. By incorporating improved DSP-based motor control strategies such as those now nearing commercialization, fully 30 to 50 percent of this energy could be saved. Power consumption by home refrigerators can be reduced by 25 percent using controllers and HVAC blower power usage can be reduced up to 80 percent.

Efficiency goes beyond the motor's energy savings. In fact, proper use of controllers offers significant savings in motor manufacture and in many related systems and products.

The increase in efficiency enabled by DSP controllers can enhance the features of many products. For example, clothes washing machines benefit greatly from enhanced control. By incorporating more sophisticated rotational control of inexpensive AC induction or reluctance motors, washing machines can gain new features that otherwise are cost prohibitive or impossible to perform. Already, features such as high-speed water extraction, gentle agitation cycles, and out-of-balance correction are found in high-end machines. Electronic controls will allow these same features to be found soon in less expensive appliances.

Earlier washing machines used a mechanical transmission to provide the various drum speeds and agitation levels for the different wash cycles, as well as the higher drum speeds required for effective water extraction. The use of a transmission allowed a single AC motor without electronic controls to perform the washer's functions - but at higher cost and with less reliability.

The newest washing machines function without a transmission, because a low cost AC induction or switched reluctance motor controlled by a sophisticated DSP or microcontroller (MCU) can provide all the normal machine cycles. In addition, electronically controlled induction or switched-reluctance motors provide a more effective and gentler agitation cycle, with not only less energy consumption but also less wear on the fabric. The spin cycle can make use of electronics to reach a higher speed than was possible before, eliminating more water and reducing drying times. More efficient cycles will mean less time required to clean clothes, less water used and, thus, less detergent.

It's in the fridge

Refrigerators will also benefit from electronic controls. For example, instead of cycling the refrigerator compressor ON, and then OFF, which requires a high starting torque, a smaller compressor with a smaller motor could be used to operate continuously at low speed and adapt its torque to maintain the desired temperature within the refrigerator without constantly starting and stopping. The result would be reduced power requirements for the compressor and overall operating costs.

With appliances, savings from improved controllers accrue over the years to easily offset the higher initial product cost brought about by the more sophisticated electronics. For washing machines, it is estimated that efficient control can provide up to 50 percent savings in electricity and water, not including savings in detergent and other energy requirements such as gas for heating water.

Speed and torque control of AC induction and switched reluctance motors used in machine tools such as mills, lathes, and drill presses, bring about an unprecedented degree of tool speed control and flexibility, while reducing mechanical complexity and machine cost.

Bells and whistles

Without electronic controls, earlier generations of machine tools required belts and pulleys, gear trains, mechanical reducers and other means to control the speed of their AC motors. These complicated mechanical devices not only added cost to the tool and reduced reliability, they also provided less precise control of the tool speed than with digital control methods. Optimum tool speed, a function of both tool and material, could usually be approached but not reached.

Sophisticated motor controls eliminate the need for a mechanical drive control system, resulting in weight reduction that reduces the cost of tool manufacture and shipping costs. Fewer mechanical components also translate to greater reliability and reduced maintenance.

Figure 1 - Meeting the needs

DSP architecture includes microcontroller features designed to support consumer product end-users.

DSP-based motor controls will likely soon lead to the creation of tools that until now could not be made. Tools with dynamically controlled cutting rates could automatically adjust to varying torque feedback encountered during machining.

Rubber meets the road

Automobiles, buses and trucks are already a significant pool of DSP applications, often for control of the various electronic systems in newer models.

DSPs designed for motor control are suitable for drive train and engine electronics, body control, and safety and security systems such as anti-lock brakes, traction and suspension, and new night vision and collision avoidance systems. Together, these applications cover nearly 90 percent of the total market for automotive semiconductors.

System designers are now faced with a greater variety of choices in controller selection, and the question of choosing a microcontroller versus a DSP is more involved. Both types of controllers provide flexibility in a wide range of applications. The MCU is still usually the best cost/performance choice for open-loop (no feedback) or electromechanical closed-loop feedback systems in applications controlling motor speed or position. However, if the motor under control is fast, has many windings, is used in a continuous torque application - or requires an additional MCU or microprocessor for control system operation - the DSP-based controllers are the best option available. Similarly, in cases where very high-speed motors are employed or the motor must be tightly controlled with a closed-loop algorithm (as in high-speed switched reluctance or low-speed traction motors) DSP-based controllers are also the best solution.

In response to the need for a more comprehensive solution to motor control, Motorola has developed a series of DSPs specifically designed for motor control, that combine the most important features of both DSPs and MCUs in a single processor.

Core architecture

Traditionally, DSPs were designed to execute signal-processing algorithms efficiently, which often led to compromises between developing a good DSP architecture and a good microprocessor architecture. Many DSP applications have used both a DSP and microcontroller, relying on the DSP for computational performance and the microcontroller for functionality. The use of extra chips adds substantially to material cost of the final product, so combining the functions of the separate chips in one becomes quite attractive in terms of cost and development time.

Combining the performance of a DSP with the broad functionality of a microcontroller becomes a significant challenge. Motorola has dealt with the problem by creating a new DSP architecture, suited for both general-purpose DSP algorithms and high performance control, using efficient microcontroller code and compiler performance. The devices combine DSP functionality with many microcontroller features, which allow motor control and overall system control (see Figure 1).

The Motorola product family built around the DSP56800 core for motor control includes the following architecture features:

• 40 million instructions per second (MIPS) with a 80 MHz clock at 4.57V - 5.5V
• Harvard architecture for high traffic data handling
• Parallel instruction set with DSP addressing modes
• Single-cycle 16 x 16-bit parallel multiplier- accumulator (MAC)
• 2 x 36-bit accumulators, including extension bits
• Single-cycle 16-bit parallel shifter
• Hardware DO and REP loops
• Three 16-bit internal core data buses and three 16-bit internal address buses
• One 16-bit peripheral interface data bus
• Instruction set support for both DSP and controller functions
• Controller style addressing modes and instructions for smaller code size
• C compiler and local variable support
• Software subroutine and interrupt stack with unlimited depth.

The DSP56800 core is a programmable CMOS 16-bit fixed point DSP designed for real-time digital signal processing and general purpose computing. The core is composed of four functional units that operate in parallel to increase machine throughput. The functional blocks - program controller and hardware looping unit, address generation unit (AGU), data arithmetic logic unit (data ALU) and bit-manipulation unit - each contains its own register set and control logic. Each functional block can operate independently and in parallel with the other three. Each functional unit interfaces with other units, with memory and with memory-mapped peripherals over the core's internal address and data buses. Therefore, simultaneously, the program controller can be fetching a first instruction, the address generation unit generating up to two addresses for a second instruction, and the data ALU performing a multiply in a third instruction.

In addition to the functional blocks, the core architecture contains three internal address buses, four internal data buses, a debug port, and clock generation circuitry.

A high-performance DSP controller design generally requires the following four attributes:

• High bandwidth parallel memory transfer capability
• An AGU that supports the parallel memory transfers and provides DSP addressing modes
• A computation unit with an adequate register set for fast algorithm calculation
• Hardware looping mechanisms for looping with no performance penalty

The Motorola architecture meets these requirements as follows:

Parallel moves: A flexible set of parallel move instructions, that allow memory accesses to occur in parallel with operations in the computation unit. Feeding data to and from the computation unit at high bandwidth keeps the computation unit busy, preventing bottlenecks in the data transfers in and out of the unit. In the present case, two types of parallel move are permitted: the single parallel move and the dual parallel read. Both of these moves execute in a single instruction cycle and occupy one word of program memory.

Figure 2 - Registering the details

Three different sets of registers corresponding to the three functional units within the DSP core.

The address generation unit: The address generation unit (AGU) is the block where all address calculations are performed. In the DSP56800 core, the AGU contains two arithmetic units and its own register set so that up to two addresses can be provided to data memory with two address updates in a single cycle. By accommodating two types of arithmetic operations (linear arithmetic - used for general-purpose address computation - or modulo arithmetic - used for creation of data structures in memory) data is manipulated by updating address registers rather than moving large blocks of data.

Fast computation with the data ALU unit: The performance of a processor's computation unit depends on how operands are accessed and stored by the unit, and on the unit's computational capabilities. Most traditional DSP designs are accumulator based, meaning that regardless of where operands originate, the results of an operation are always stored in an accumulator. Operations are performed so that one operand is in the accumulator, except for multiplication, where an accumulator is not allowed as one multiplier input.

Computational efficiency is enhanced by a greater number of registers and more orthogonal structure, where results of arithmetic operations can be written back to any of the data ALU's five registers. The data ALU input also allows for immediate value operands, significantly increasing the power of the register set by allowing increments on any register while providing other registers for arithmetic computations. Accumulators may be used as inputs to the multiplier, or for accumulation. This technique also reduces memory accesses because intermediate results do not need to be temporarily stored in memory. The core design is not pipelined, so that the result of a multiplication or multiply-accumulate is available after one instruction cycle instead of two.

Looping mechanisms: DSP and other numeric computation programs often force much of the processor execution to be spent in small, numerically intensive computation loops with a large amount of memory traffic. For that reason, it becomes necessary to provide a flexible set of parallel moves with a powerful register set. It is also important that execution time due to looping itself be minimized. The DSP56800 core uses a hardware looping mechanism that automatically performs the looping without adding extra computation time, referred to as "no overhead looping." Flexible hardware looping mechanism is achieved by providing a hardware DO looping mechanism, which can loop on any number of instructions without adding execution time. Unlike earlier no-overhead loop designs, the loop mechanism is interruptible and provides a REPEAT loop capability that can be nested within the DO loop mechanism.

The core of the problem

The programming model for the core is separated into three different sets of registers corresponding to the three functional units within the DSP core (see Figure 2). Each functional unit has a full set of registers to perform its tasks.

The architecture described here allows operations directly with immediate data or on memory. The use of immediate data helps to decrease register usage because arithmetic operations can be performed directly with immediate data, confining registers to the storage of important variables and intermediate results instead.

The core's MOVE instructions and addressing modes are designed to be general, to ease the task of programming and improve efficiency. The complete set of addressing modes supports eight different addressing modes for any MOVE instruction accessing data memory or an on-chip memory mapped peripheral register. Additional addressing modes are available on a subset of frequently accessed DSP core registers, including the registers in the data ALU and all the pointers in the AU.

In addition to the hardware looping described above, software looping is an important capability in DSP architectures. The core can implement software loops using registers in either the AGU or data ALU for the loop counter. The ability to implement loops using a memory location for the loop count, which makes available the full register set for algorithm computation, also proves useful.

Instead of the traditional hardware stack found on most DSP architectures, the DSP56800 core implements its stack using a true stack pointer in memory.

This allows for unlimited nesting of subroutines and interrupts and also supports the structured programming techniques generally found only on high-end controllers, such as parameter passing to subroutines and local variables. Together with the addressing modes, the software stack and stack pointer are useful for both assembly language programming and higher-level language compilers.

The core architecture reduces code size, both for DSP programs and controller code. The ability for instructions to work directly on memory locations, looping mechanism, orthogonal set of move instructions and addressing modes, and the ability to load immediate values directly into memory locations, all contribute to reductions in code size for general purpose computing. Code size is reduced for DSP algorithms by the parallel move instructions, complete register sets, and the ability to write results back into any of the data ALU registers. Code density is also improved by the ability to perform arithmetic operations directly with immediate data or memory locations. Initial results indicate reductions of a third to a half in program code size compared to compilers for traditional DSP architectures.

cessing and peripherals

The interrupt unit on the DSP56800 uses a vectored interrupt scheme, allowing for fast servicing of interrupts, and is expandable to support future core-based designs. The present design supports 13 different interrupt sources: seven interrupt channels for seven different on-chip peripherals, two external interrupts and four interrupt sources from the DSP core. From the interrupt sources, execution can be vectored to any of up to 64 different interrupt vectors. Each maskable interrupt source can be individually masked, or all maskable interrupts can be masked in the status register.

Combining the core with peripheral features allows highly integrated products to be created to provide economical systems solutions for motor control applications. The members of the DSP56800 family contain multi-channel A/D, PWM, CAN, quadrature encoders, and a voltage regulator on a single chip. The peripherals simplify motor control system and software design such as dead-time insertion, distortion correction, and synchronization with the A/D converter. The quadrature encoder provides debounce, shaft position, and velocity measurements while minimizing the use of external board components. Each product utilizes FLASH memory for program, data and boot memories. This feature allows remote programming, shortens design cycle time, and eliminates traditional mask charges for program ROM while allowing flexibility in system design reuse.

Software that has been optimized and fully tested at the driver, algorithm, and application level will also reduce overall design time. Providing libraries utilizing a common API eases the migration of legacy code both from 8-bit MCU applications and to higher performance DSP cores of the future.

Supporting apps

The DSP56800 family is supported by software and hardware development tools and includes an integrated software development environment, an EVM target platform for software development, modular motion control development hardware, visual analysis tools for monitoring and modifying motor control parameters in real time, and embedded software.

In summary, the DSP56800 core architecture is suitable for cost sensitive applications such as consumer applications such as servo and AC motor control.

Other possible applications include modems, digital wireless messaging, digital answering machines, and digital cameras. High-performance DSP features and general purpose instruction set make the architecture useful in applications requiring low cost, low power consumption, and efficient program code.

Rich Hoefle, a 15-year Motorola veteran, has held several positions with the company: applications engineer, senior field sales rep, regional engineering manager, market development manager, and regional technology manager. Currently, he is an applications engineering manager for the DSP standard products division (Tempe, AZ).

To voice an opinion on this or any other article in Integrated System Design, please e-mail your comments to sdean@cmp.com.